Co-optimization of buffer layer and FTL in high-performance flash-based storage systems

NAND flash-based storage devices have rapidly improved their position in the secondary storage market ranging from mobile embedded systems to personal computer and enterprise storage systems. Recently, the most important issue of NAND flash-based storage systems is the performance of random writes as well as sequential writes, which strongly depends on their two main software layers: a Buffer Management Layer (BML) and a Flash Translation Layer (FTL). The primary goal of our study is to highly improve the overall performance of NAND flash-based storage systems by exploiting the cooperation between those two layers. In this paper, we propose an FTL-aware BML policy called Selective Block Padding and a BML-based FTL algorithm called Optimized Switch Merge, which overcome the limitations of existing approaches on performance enhancement. When using both the proposed techniques, evaluation results show that the throughput is significantly increased over that of previous studies. H. Shim ( ) · S. Maeng Computer Science Department, Korea Advanced Institute of Science and Technology (KAIST), 335 Gwahangno, Yuseong-gu, Daejeon, Republic of Korea e-mail: [email protected] S. Maeng e-mail: [email protected] D. Jung · J. Kim Memory Division, Samsung Electronics Co., Ltd., Hwaseong, Republic of Korea D. Jung e-mail: [email protected] J. Kim e-mail: [email protected] J.-S. Kim School of Information and Communication Engineering, Sungkyunkwan University (SKKU), 300 Cheoncheon-dong, Jangan-gu, Suwon, Republic of Korea e-mail: [email protected]